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MP7226 1 rev. 2.00 features ? mps pioneered segmented dac approach ? four 8-bit dacs with buffer amplifiers ? bipolar amplifier inputs for low noise and drift ? operates with single or dual supplies ? m p compatible (95ns wr ) ? no external adjustments required ? power-on-reset function ? specified for 5 to 15 v operation ? esd protection: 2000 volts minimum ? latch-up proof ? octal available: mp7228 bicmos fixed, quad, voltage output, single or dual supply 8-bit digital-to-analog converter applications ? function generators ? automatic test equipment ? process controls benefits ? reduced board space; lower system cost ? reduced system errors due to excellent dac-to-dac matching and tracking ? easy to design with microprocessors ? stable, high reliability through advanced processing ? lower 1/f noise increases useful dynamic range general description the MP7226 contains four 8-bit voltage-output digital-to- analog converters, with bicmos output buffer amplifiers and interface logic on a monolithic chip. separate on-chip latches are provided for each of the four d/a converters. the control logic is speed compatible with most 8-bit microprocessors. all digital inputs are ttl/cmos(5v) compatible. the MP7226 is manufactured using advanced thin film resis- tors on a double metal bicmos process. the MP7226 incorpo- rates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. the MP7226 maintains 8-bit accuracy over the full operat- ing temperature range without laser trim or external adjust- ments. simplified block diagram latch 1 dac 1 + 1 dac 2 + 2 dac 3 + 3 dac 4 + 4 v out1 v out2 v out3 v out4 v ref v dd latch 2 latch 3 latch 4 v ss agnd msb lsb data (8 bit) wr a1 a0 control logic d a t a b u s dgnd
MP7226 2 rev. 2.00 ordering information package type temperature range inl (lsb) part no. dnl (lsb) full scale error (lsb) plastic dip plcc soic 40 to +85 c MP7226kn MP7226kp MP7226ks 40 to +85 c 40 to +85 c 1 1 plastic dip 40 to +85 c MP7226ln* 1/2 plcc MP7226lp* 40 to +85 c soic MP7226ls* 40 to +85 c *contact factory for availability. 1 1/2 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1/2 1 1/2 pin configurations 20 pin pdip (0.300o) n20 a0 a1 db0 (lsb) db1 db2 db3 20 pin soic (jedec, 0.300o) s20 v out2 v out1 v ss v ref agnd dgnd db7 (msb) db6 db5 db4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd v out3 v out4 20 1 11 10 2 3 4 5 6 7 15 14 13 12 17 16 8 9 19 18 see pin out at left 3 2 1 20 19 9 10111213 4 5 6 7 8 18 17 16 15 14 see pin out at far left 20 pin plcc p20 wr see packaging section for package dimensions pin out definitions 1v out2 dac 2 voltage output 2v out1 dac 1 voltage output 3v ss negative power supply (0 v to 5 v) 4v ref reference input voltage 5 agnd analog ground 6 dgnd digital ground 7 db7 data input bit 7 (msb) 8 db6 data input bit 6 9 db5 data input bit 5 10 db4 data input bit 4 pin no. name description 11 db3 data input bit 3 12 db2 data input bit 2 13 db1 data input bit 1 14 db0 data input bit 0 (lsb) 15 wr write (active low) 16 a1 dac address bit 1 17 a0 dac address bit 0 18 v dd positive power supply (+5 to +15 v) 19 v out4 dac 4 voltage output 20 v out3 dac 3 voltage output pin no. name description
MP7226 3 rev. 2.00 electrical characteristics single or dual supply operation (v dd = +10.8 v to 16.5 v, v ss = 0 v or 5 v 10%, agnd = 0 v, dgnd = 0 v, v ref = +2 v to +10 v, r l = 2k w , c l = 100pf unless otherwise noted) 25 c tmin to tmax parameter symbol min typ max min max units test conditions/comments static performance resolution (all grades) n 8 8 bits integral non-linearity inl lsb (relative accuracy) k 1 1 end point linearity spec l 1/2 1/2 differential non-linearity dnl lsb all grades monotonic over full k 1/2 3/4 temperature range. l 1/2 3/4 total unadjusted error 2 lsb v dd = 15 v 10%, v ref = +10 v k 2 2 l 1 1 full scale error 3 lsb v ref = +10 v typ. tempco is k 1 1 5 ppm/ c l 1/2 1/2 zero code error mv ta = 25 c typ. tempco is k 20 30 30 m v/ c l 15 20 output load resistance 2 2 k w v out = +10 v dynamic performance 4 voltage output slew rate 2 4 2 v/ m s voltage output settling time 4 5 m sv ref = +10 v; settling time to 1/2 lsb digital feedthrough 25 nvs code transition all 0s to all 1s v ref = 0 v, wr = v dd digital crosstalk 5 25 nvs code transition all 0s to all 1s v ref = +10 v, wr = 0 v reference input reference input range 1 1 10 1 10 v limitation: v ref v ss < 11 v reference input resistance r in 22k w min r in at code 149 10 reference input capacitance 4 500 pf occurs when all dacs are loaded with all 1s ac feedthrough 70 db v ref = 10 khz, 5 v p-p sinewave digital inputs input high voltage v inh 2.4 2.4 v input low voltage v inl 0.8 0.8 v input leakage current i lkg 1 1 m av in = 0 v or v dd input capacitance 4 88pf input coding binary
MP7226 4 rev. 2.00 electrical characteristics (cont'd) 25 c tmin to tmax parameter symbol min typ max min max units test conditions/comments power supply v dd range 10.8 16.5 10.8 16.5 v for specified performance v ss range (dual supplies) 8 0 5.5 0 5.5 v for specified performance i dd 12 14 ma outputs unloaded; v in =v inl or v inh i ss (dual supplies) 10 12 outputs unloaded; v in =v inl or v inh switching characteristics 4, 6, 7 address to wr setup time, t1 t as 00ns address to wr hold time, t2 t ah 00ns data valid to wr setup time, t3 t ds 70 95 ns data valid to wr hold time, t4 t dh 10 10 wr pulse width, t5 t wr 95 120 ns notes: specifications are subject to change without notice 1 v out must be less than v dd by 3.5 v to ensure correct operation. 2 total unadjusted error includes zero code error, relative accuracy and full-scale error. 3 calculated after zero code error has been adjusted out. 4 sample tested at 25 c to ensure compliance. 5 the glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 all input rise and fall times are measured from 10% to 90% of +5 v, t r = t f = 5 ns. 7 timing measurement reference level is (v inh + v inl )/2.
MP7226 5 rev. 2.00 electrical characteristics single & dual 5 v supply operation (v dd = +5 v 5%, v ss = 0 v to 5 v 10%, v ref = +1.25 v, agnd = 0 v, dgnd = 0 v, r l = 2k w , c l = 100pf unless otherwise noted) 25 c tmin to tmax parameter symbol min typ max min max units test conditions/comments static performance resolution (all grades) n 8 8 bits integral non-linearity inl lsb (relative accuracy) k 2 2 end point linearity spec l11 differential non-linearity dnl lsb all grades monotonic over full k 1 1 temperature range. l 1 1 total unadjusted error 2 4 lsb v dd = 5 v 5%, v ref = 1.25 v full scale error 3 lsb v ref = +1.25 v k 4 4 l 2 2 zero code error 20 mv output load resistance 2 k w v out = +10 v dynamic performance 4 voltage output slew rate 2 4 v/ m s voltage output settling time 4 m sv ref = +1.25 v; settling time to 1/2 lsb digital feedthrough 25 nvs code transition all 0s to all 1s v ref = 0 v, wr = v dd digital crosstalk 5 25 nvs code transition all 0s to all 1s v ref = +1.25 v, wr = 0 v reference input reference input range 1 1.6 1 1.6 v v out must be < v dd by 3.2v reference input resistance r in 22k w reference input capacitance 4 500 pf occurs when all dacs are loaded with all 1s ac feedthrough 70 db v ref = 10 khz, 1/2 v p-p sinewave digital inputs input high voltage v inh 2.4 2.4 v input low voltage v inl 0.8 0.8 v input leakage current i lkg 1 1 m av in = 0 v or v dd input capacitance 4 88pf input coding binary
MP7226 6 rev. 2.00 electrical characteristics (cont'd) 25 c tmin to tmax parameter symbol min typ max min max units test conditions/comments power supply v dd range 4.75 5.25 4.75 5.25 v for specified performance i dd 8 8 ma outputs unloaded; v in =v inl or v inh i ss (dual supplies) 6 6 outputs unloaded; v in =v inl or v inh switching characteristics 4, 6, 7 address to wr setup time, t1 t as 00ns address to wr hold time, t2 t ah 00ns data valid to wr setup time, t3 t ds 70 95 ns data valid to wr hold time, t4 t dh 0 wr pulse width, t5 t wr 95 120 ns notes: specifications are subject to change without notice 1 v out must be less than v dd by 3.5 v to ensure correct operation. 2 total unadjusted error includes zero code error, relative accuracy and full-scale error. 3 calculated after zero code error has been adjusted out. 4 sample tested at 25 c to ensure compliance. 5 the glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 all input rise and fall times are measured from 10% to 90% of +5 v, t r = t f = 5 ns. 7 timing measurement reference level is (v inh + v inl )/2. absolute maximum ratings (t a = +25 c unless otherwise noted) 1, 2 v dd to agnd, dgnd 0 to +17 v . . . . . . . . . . . . . . . . . . . . . . digital input voltage to dgnd 0.5 to v dd +0.5 v . . . . . . . . v ref to agnd, dgnd 0.5 to v dd +0.5 v . . . . . . . . . . . . . . v ss to agnd, dgnd +0.5 to 7 v . . . . . . . . . . . . . . . . . . . . . agnd to dgnd + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (functionality guaranteed + 0.5 v) storage temperature 65 c to +150 c . . . . . . . . . . . . . . . . . lead temperature (soldering, 10 seconds) +300 c . . . . . . package power dissipation rating to 75 c pdip, soic, plcc 900mw . . . . . . . . . . . . . . . . . . . . . . . . derates above 75 c 12mw/ c . . . . . . . . . . . . . . . . . . . . . notes: 1 stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2 any input pin which can see a value outside the absolute maximum ratings should be protected by schottky diode clamps (hp5082-2835) from input pin to the supplies. all inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100ma for less than 100 m s.
MP7226 7 rev. 2.00 d/a converter section the MP7226 contains four matched, 8-bit, voltage-mode dig- ital-to-analog converters (dacs) which incorporate an mps pioneered unique bit decoding technique. this decoding scheme reduces the maximum binary weight carried by any re- sistor switch, reducing the accuracy required of the switches and resistor network. in the MP7226, the first three msbs are decoded into three equal current sources, each contributing 25% of the full scale output current. decoding two bits to three, a 1% change in any one of the converter's three decoded current sources affects the output by no more than 0.25% of full scale, compared with 0.5% in a con- ventional r-2r type cmos dac. the output voltages have the same polarity as the reference voltage, allowing single supply operation. the voltage refer- ence range is from +2v to +10v. each dac uses a highly-stable, thin-film, ladder network and high-speed nmos switches. figure 1. shows a simplified circuit diagram for one channel. 2r 4r 4r 4r 4r 2r 2r switch drivers figure 1. simplified d/a circuit diagram + 2 to 3 decoder 4r 4r v ref agnd shown for all 1s on dac v out v ref input the v ref and agnd are common to all four dacs and set the full-scale output. the input impedance of the v ref pin is the parallel combination of the four individual dac reference imped- ances and is code dependent. this impedance varies from 2k w to 500k w . therefore, it is very important that the external refer- ence source output impedance is low enough so that its output voltage will not be affected by the varying digital code. due to transient currents at the v ref input during digital code changes, a 0.1 m f or greater decoupling capacitor on that v ref input is recommended. the input capacitance at the v ref pin is also code dependent and typically varies from less than 120pf to 350pf. each v out voltage can be represented by a digitally pro- grammable voltage source using the following expression : v out = dn x v ref /256 where dn is the decimal equivalent to the digital input code and can vary from 0 to 255. output buffer amp each d/a converter output is buffered by a unity gain nonin- verting bicmos amplifier which has slew rate greater than 2 v/ m s . the output buffer settles to 1/2 lsb in less than 4 m s when driving a load of 2k w in parallel with 100pf with a full scale transi- tion from 0v to +10v or from +10v to 0v . the buffers can drive 2k w and 500pf to 10v levels without oscillation. a simplified circuit diagram of the output buffer is shown in figure 2. the input stage is provided by bicmos pnp transis- tors with resulting lower input offset voltage, offset voltage drift over time and noise when compared to mos process . the am- plifier output stage uses a substrate npn bipolar device to pro- vide a low output impedance, high-output current capability. the MP7226 is specified for single or dual power supply op- eration, with only the buffer amplifier outputs using v ss supply current . operating the MP7226 from dual supplies will improve the negative going output settling time near ground. in dual sup- ply voltage operation , the output amplifier can sink 500 m a when v out = 0 v.
MP7226 8 rev. 2.00 figure 2. simplified output buffer amplifiers v dd v in agnd v ss output the amplifiers outputs may be shorted to ground. however, the power dissipation of the package should not exceed the maximum limit. digital inputs all of the digital inputs to this dac maintain ttl level inter- face compatibility and can also be driven directly with 5v cmos logic inputs. the digital inputs are esd protected to a rating of 2000 volts. digital interface logic the MP7226 allows direct interface to most microprocessor buses without additional interface circuitry. figure 3. shows the input control logic circuit diagram and table 1. shows the control logic truth table and operation for wr , a1, a0. the address lines a0, and a1 determine which dac will accept the input data. the wr input determines whether the selected dac is transparent (output follows the in- put), latched, or no operation. the wr input will also inhibit power on reset of the dac latches to 0, if its initial state = 0 after 5 m s of power. figure 4. shows the write cycle timing diagram. when the wr signal is low, the input latch of the selected dac is transparent, and the dac's output corresponds to the value present on the data bus. on some data buses, data is not always valid for the entire period that the wr signal is low and can cause unwanted data at the output. ensuring that the write pulse (wr ) conforms to the data hold time, (t4) spec will prevent this problem. figure 3. input control logic wr to dac1 latch enable to dac2 latch enable to dac3 latch enable to dac4 latch enable a0 a1 1 of 4 decoder h l l l l x l l l h h x l l h l h wr a1 a0 operation no operation; device not selected dac 1 transparent dac 1 latched dac 2 transparent dac 3 transparent dac 4 transparent table 1. truth table figure 4. write cycle timing diagram address data wr t as t ah t wr t ds t dh v inh v inl 5 v 0 v 5 v 0 v 5 v 0 v note: when the wr signal is low, the input latch of the se- lected dac is transparent and any invalid data at this time will cause erroneous output.
MP7226 9 rev. 2.00 applications information power on reset at power up, all inputs are reset to 0 v if wr = 1. for wr = 0, the addressed dac will receive input data. power supply the MP7226 can operate with either a single or dual power supply. improved zero-code settling error can be obtained by using dual power supplies. the dual power supply specifica- tions are a positive supply (v dd ) range of +10.5v to +16.5v, and a 5v supply (v ss ) . the single power supply specifications are a positive supply (v dd ) range of +10.5v to +16.5v, or range of +4.75v to 5.5v . the specified reference voltage (v ref ) range under these conditions is from +2v to v dd 4v. for those appli- cations requiring +10v at the output (v ref = +10v), v dd must be +14v minimum to meet data sheet limits . 8-bit performance is guaranteed for single supply operation (v ss = 0v); however, zero code output sink capability is improved with v ss = 5v. for adequate dac and buffer operation, v ref must always be be- low v dd by at least 3.5v. power supply decoupling the power supplies used with the MP7226 should be well regulated and filtered. local power supply decoupling consist- ing of a 10 m f tantalum capacitor in parallel with a 0.01 m f ce- ramic is recommended. the decoupling capacitors should be connected between the v dd and agnd, and between v ss and agnd if v ss = 5v. unipolar output operation in this configuration, the reference voltage is the same polar- ity as the output voltage. since the reference voltage must al- ways be positive with respect to gnd, the output can only be 0 or positive. table 2. shows the code relationship for the part in unipolar operation table 2. unipolar code table 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 digital input analog output, v out

table 3. bipolar code table 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 digital input analog output 0 v
MP7226 10 rev. 2.00 v ref v ref v out v ss agnd dac + v out r2 r1 v out = d n x v ref x (1+r2/r1) v ref x r2/r1 if r1 = r2 v out = v ref x (2d n 1) where d n is the digital input code and can vary from 0 to 255 figure 5. bipolar output circuit + bipolar binary operation the bipolar mode configuration for each dac requires one external op-amp and two resistors per channel. figure 5. shows a typical bipolar operation circuit using the MP7226. table 3. shows the code relationship for the circuit of figure 5. assuming r1 = r2 . ac reference signal an ac signal can be applied to the reference of the MP7226 for multiplying capability within the upper (+10v) and lower (+2v) limits of the reference voltage input, with either single or dual supplies . this signal must be level shifted or ac coupled with proper bias level before being applied to the reference in- put. figure 6. shows techniques for applying an ac signal to the MP7226. since all four dacs share a common reference, they will all share this ac modulated reference. input frequencies up to 50khz will typically be distorted less than 0.1% . v ref v dd v out 5 v or gnd agnd dac + r1 figure 6. ac reference input signal circuit (ac couple) + r2 c ac reference input +4 v 4 v +15 v dc offset +10 v +2 v dc offset = v dd (+15) x r2/r1+r2 v ss
MP7226 11 rev. 2.00 + figure 7. digitally programmable offset adjustment circuits dac output v offset v out v out = d n x v ref + v offset where d n is the digital input code and can vary 0 to 255 + dac output1 v out v out = d n1 x v ref + d n2 x v ref where d n is the digital input code and can vary 0 to 255 dac output2 rr r r rr r r v ref v dd v out 5 v or gnd agnd dac + figure 8. digitally programmable ac reference input signal circuit (dc couple) + ac reference input dac or dc voltage +15 v v ss offsetting dac outputs figure 7. shows examples of offset circuits. dac offset effects when using the device in single supply applications, and minimum reference voltage, there is a possibility that the dac output will not change when the code is incremented from 0. once the dac has reached the offset voltage of the output buffer, the dac output will begin to increment in a normal opera- tion. 5v operation the MP7226 can be operated with a single power supply (v dd = +5v ) or dual power supplies ( v dd = +5v and v ss = 5v) . the reference voltage range is reduced along with some performance parameter degradation. however the dnl of each dac remains at 1 lsb guaranteeing monotonicity.
MP7226 12 rev. 2.00 performance characteristics graph 1. power supply current vs. temperature graph 2. relative accuracy vs. digital code
MP7226 13 rev. 2.00 20 lead plastic dual-in-line (300 mil pdip) n20 20 1 11 10 d eb 1 a 1 e 1 a c e a l b q 1 seating plane symbol min max min max inches a 0.200 5.08 a 1 0.015 0.38 b 0.014 0.023 0.356 0.584 b 1 (1) 0.038 0.065 0.965 1.65 c 0.008 0.015 0.203 0.381 d 0.945 1.060 24.0 26.92 e 0.295 0.325 7.49 8.26 e 1 0.220 0.310 5.59 7.87 e 0.100 bsc 2.54 bsc l 0.115 0.150 2.92 3.81 a 0 15 0 15 q 1 0.055 0.070 1.40 1.78 s 0.040 0.080 1.02 2.03 millimeters s note: (1) the minimum limit for dimensions b1 may be 0.023o (0.58 mm) for all four corner leads only.
MP7226 14 rev. 2.00 symbol min max min max a 0.097 0.104 2.464 2.642 a 1 0.0050 0.0115 0.127 0.292 b 0.014 0.019 0.356 0.483 c 0.0091 0.0125 0.231 0.318 d 0.500 0.510 12.70 12.95 e 0.292 0.299 7.42 7.59 e 0.050 bsc 1.27 bsc h 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 l 0.016 0.035 0.406 0.889 a 0 8 0 8 inches millimeters e 20 11 20 lead small outline (300 mil jedec soic) s20 10 d e h b a l c a 1 seating plane a h x 45
MP7226 15 rev. 2.00 a 0.165 0.180 4.19 4.57 a 1 0.100 0.110 2.54 2.79 a 2 0.148 0.156 3.76 3.96 b 0.013 0.021 0.330 0.533 c 0.008 0.012 0.203 0.305 d 0.385 0.395 9.78 10.03 d 1 (1) 0.350 0.354 8.89 8.99 d 2 0.290 0.330 7.37 8.38 d 3 0.200 ref 5.08 ref. e 1 0.050 bsc 1.27 bsc 20 lead plastic leaded chip carrier (plcc) p20 symbol min max min max inches millimeters 1 d d 1 d 2 b e 1 a a 1 c d d 1 seating plane d 3 note: (1) dimension d 1 does not include mold protrusion. allowed mold protrusion is 0.254 mm/0.010 in. a 2
MP7226 16 rev. 2.00 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1993 exar corporation datasheet april 1995 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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